1. Field of the Invention
The present invention relates to a data processing apparatus and method for testing the stability of memory cells in a memory device.
2. Description of the Prior Art
Memory devices are typically formed as an array of memory cells. Each memory cell is typically formed of a plurality of components such as transistors, and these individual components may be constructed in a variety of ways. One known approach involves forming the cells using transistors that have a body region insulated from a substrate. The body region comprises the channel material in which a channel is established between the source and drain of the transistor below the gate of the transistor. By using transistors having a body region insulated from the substrate, it has been found that this reduces the capacitive loading on the transistor terminals when compared with transistors formed from non-insulated technologies where the channel material is formed on a conducting substrate. This reduced capacitive loading can give rise to increased switching speed of the transistors and lower power dissipation.
One known technology that can be used to produce transistors having a body region insulated from the substrate is referred to as Silicon-On-Insulator (SOI) technology, where the SOI channel material is formed within a region of a thin superficial silicon layer above an oxide insulating layer and located under the gate of the transistor, reducing resistive leakage to the substrate and capacitive loading by the substrate. Consequently, this body region is not biased to any known voltage, and its voltage can vary depending on charges arising from diode leakage, coupling capacitance with the gate, drain or source, impact ionisation, etc. Additionally, the voltage on the body region becomes dependent on the previous circuit activity, which is typically referred to as the “history effect”. This variation in voltage on the body region can have an impact on the behaviour of a memory cell constructed using such transistors, since any change in the body voltage will typically modify the threshold voltage of the transistor, thus modifying the current passing through the transistor and the switching speed of the transistor.
When such transistors are used to form the memory cells of a memory device, it has been found that the above-mentioned body region history effect can adversely affect the stability of memory cells in certain situations. It is important when producing memory devices for the individual memory cells to have the required stability to ensure effective retention of data (stability sometimes being measured in terms of static noise margin (SNM)), whilst also having required write-ability (WM) to ensure that new data values can be stored in the cells within the time period allowed for a write operation. Whilst the increased switching speed and low power dissipation characteristics resulting from the use of transistors having a body region insulated from the substrate clearly make the use of such transistors very attractive, it is important to detect the presence of any memory cells in the memory device whose stability is unacceptably adversely affected by the history effect, as otherwise those memory cells may fail in use. Typically, memory devices are constructed with a number of redundant memory cells which can be switched in in place of memory cells that are identified to be defective, and accordingly if such unstable memory cells could be identified at production time, redundant memory cells can be switched in in their place to ensure that the memory device will operate correctly.
Accordingly, it is known to perform a number of test procedures on memory devices at the time of production to seek to identify defective memory cells, one category of such defective cells being those whose stability drops below a predetermined level due to the earlier-mentioned history effect.
One type of test procedure that can be performed to seek to identify defective cells takes the form of a Built-In Self Test (BIST) procedure whereby a number of test patterns are executed to seek to detect defective cells. Each test pattern typically causes a sequence of access requests to be issued to the memory device. For transistors having a body region insulated from the substrate, it has been found that the stability of a memory cell constructed using such transistors is at its lowest point immediately after a write operation takes place, and over time the voltage on the body region will re-stabilise increasing the stability of the memory cell. In normal use, this instability of the memory cell at the end of a write operation could in some cells cause a failure of the memory cell if a read operation occurs to that memory cell immediately following the write operation. Whilst that read operation may itself correctly read the data, it may cause the data value stored in the memory cell to flip during the read operation, such that a subsequent read operation from the memory cell would obtain incorrect data.
To keep test time and cost to a minimum, it is desirable to use test patterns which can be used to detect a variety of defects in the memory device. Accordingly, when testing for the above cell stability problem, one known prior art technique involves using pre-existing test patterns developed to detect other defects. Whilst such test patterns may write to a particular memory cell and then later in the test read from that memory cell a first time, and later read from that memory cell a second time, hence implementing the write, read, read pattern required to detect unstable memory cells, the amount of time between the initial write operation and the first read operation will vary dependent on the particular test pattern used. The longer the gap between the initial write operation and the first of the subsequent read operations, the more the voltage on the body region will have re-stabilised increasing the stability of the memory cell, and hence the less likely the memory cell will be to flip. Accordingly, using such pre-existing test patterns, the worst case stability situation due to history effects will not in fact be present, and accordingly such an approach will not identify all of the memory cells that may malfunction in use due to stability problems caused by the history effect.
An alternative approach would be to develop a dedicated test pattern solely for testing the stability problem introduced by the history effect. In particular, a test pattern could be developed where every write operation is immediately followed by two read operations at the same address (or at least the first read operation immediately follows the write operation). However, as mentioned earlier, in many applications it will often be determined to be too expensive to develop a dedicated test pattern just for testing this particular stability problem, both in terms of the time taken to produce the separate test pattern, and also the increase in overall test time taken for each memory device as a result of having to execute this additional separate test.
An alternative approach developed by IBM is referred to by IBM as a “flood mode” used to test stability in SOI transistors. In accordance with the flood mode, a write operation begins in the usual manner by selecting a particular word line in the memory array, and then lowering the voltage on one of the bit lines connected to an addressed column in the memory array. However, when the write operation is completed, whilst the bit lines are then precharged back to a logic one level in the usual way for a write operation, the word line continues to be enabled, as a result of which a condition arises where both of the bit lines are precharged to the logic one voltage level and the word line is still enabled. This represents the most unstable situation having regards to the history effect. Accordingly, this condition is maintained for a predetermined period of time, and if the memory cell's stability is below an acceptable level, it is likely that the data value in the cell will flip during the duration of the flood mode. Subsequently, the data stored in the memory cell is subjected to a read operation, and it is determined whether the data value read from the memory cell is the same as the data value written to the memory cell. If not, the memory cell is identified as defective.
There are a number of problems with this approach. One drawback is that the stressing of the memory cell depends on the duration of the flood mode, and this timing is difficult to tune on silicon. If the flood mode is maintained for too short a period of time, some unstable memory cells will not be detected, and conversely if the flood mode is maintained for too long, more memory cells will be detected than would actually fail in normal operation. Furthermore, due to the time spent at the end of each write operation to implement the flood mode, such an approach gives rise to a test operation that is more lengthy than desired.
Whilst memory cells constructed using SOI transistors or the like can have cell stability problems, since as a result of the body region history effect the cell instability is at its worst immediately following a write operation, and subsequently improves over time, such cell stability problems are not limited to memory cells using such transistors, and more generally the above problems can manifest themselves in association with any memory cells where the cell stability is adversely affected by a write operation.
Accordingly, it would be desirable to provide an improved technique for testing the stability of memory cells in a memory device, and in particular for testing for cell instability following a write operation.